1. Field of the Invention
The disclosure relates in general to a method of manufacturing a three-dimensional (3D) stacked semiconductor structure and a structure manufactured by the same, and more particularly to the method for manufacturing the structure having dielectric supports for multi-layered pillars, thereby strengthening the overall construction.
2. Description of the Related Art
A nonvolatile semiconductor memory device is typically designed to securely hold data even when power is lost or removed from the memory device. Various types of nonvolatile memory devices have been proposed in the related art. Also, manufactures have been looking for new developments or techniques combination for stacking multiple planes of memory cells, so as to achieve greater storage capacity. For example, several types of multi-layer stackable NAND-type flash memory structures have been proposed. However, the typical 3D memory structure suffers from several problems.
For the conventional 3D stacked semiconductor structure and manufacturing method, the easily bended or collapsed problems occurred often due to higher aspect ratio. FIG. 1 schematically shows the bended pillars occurred in the conventional 3D stacked semiconductor structure. It has been studied that the structure deformation of the pillar is related to the height H and the width L of pillar. In FIG. 1, γ represents surface tension, E represents Young modulus, and δ represents structure deformation, wherein
  δ  =      3    ⁢    γ    ⁢                  ⁢    cos    ⁢                  ⁢    θ    ⁢                            H          4                          dEL          3                    .      If the pillars of the 3D stacked semiconductor structure are tall and narrow, it is easily bended or collapsed.
Also, the multi-layered pillars of the 3D stacked semiconductor structure are oxide-and-polysilicon (O-P) stacks, which exhibit unbalanced stress, and are easily collapsed or bended during manufacturing processes. Furthermore, the oxide is dielectric and polysilicon is conductor, and the vertical sidewalls of the O-P stack shows a zig-zag profile, which may have considerable effects on the electrical properties of the 3D stacked semiconductor structure.